A degree. in Computer Science, Computer Engineering or Electrical Engineering
At least 5 years of experience in hardware modeling development
Hands on C++ and OOD/OOP
Excellent knowledge in general hardware micro architecture
Knowledge in CPU micro architecture and Cache system – an advantage
Knowledge in data center and big data applications – an advantage
Experience as a hardware pre-silicon verification architecture – an advantage

B.Sc/M.Sc in Electrical or Computer Engineering or Computer Science
At least 3 years of SoC verification experience with SystemVerilog, UVM and/or Specman.
In depth understanding of overall verification methodologies
Understanding of verification and design practices
Background in Networking IPs and SoC architecture

תואר ראשון או שני בהנדסת חשמל אלקטרוניקה או אקוויוולנטי.
7 + שנות ניסיון כמהנדס וראיפיקציה.
ניסיון וידע ב System Verilog.
5+ שנות ניסיון בתחום רכיבים מתוכנתים
ניסיון וידע בכתיבת קוד ב TCL / PERL / PYTHON – חובה

3-5 Years in Logic Design/Verification
Advantage for experienced verification engineer
Advantage for DFT verification / design engineer
Good capabilities in SW programming, knowledge in C/C++ language – an advantage
Experience with Verilog/VHDL development language – an advantage

BSc in Electrical Engineering, from a well-known university.
5-12 years of experience in full chip and block level logic verification. SOC Architecture design and implementation knowledge is an advantage. Working experience with
Strong verification skills including a good knowledge and understanding of different verification methodologies (random vs. directed testing, fullchip vs. module-level)
Working knowledge and experience with Verilog
MCU/Flash products – advantage.

B.Sc. in Electrical Engineering (from known university).
Minimum 4 years of experience in SoC Verification.
Knowledge and experience in System Verilog or ‘e’ (Specman) languages.
Vast knowledge of verification flow (block level & full chip verification).

B.Sc. in Electrical Engineering
7+ years in VLSI verification
Experience in System Verilog
Experience in verification of processors is an advantage
Experience in C/C++ programming is an advantage

תואר ראשון בהנדסת חשמל ואלקטרוניקה, ממוצע 85+, מאחת האוניברסיטאות המובילות
0-5 שנות ניסיון בפיתוח חומרה

B.Sc in Electrical or Computer Engineering or Computer Science is required
Advanced knowledge of digital logic design.
Must have done formal property proofs on several blocks
Solid understanding of formal verification technologies and abstraction techniques.
Knowledge and experience in interpreting hardware specifications and
using temporal logic assertion-based languages.

3+ years experience in SoC Verification
You will need to have advanced knowledge of SoC architecture/design & in-depth knowledge of verification flow
Must have a clear understanding and proven experience in advanced verification process, including dynamic, coverage based and formal methods
Familiarity with verification environments, VMM, SystemVerilog