BSc in Electrical Engineering.
3 – 5 years of experience running large scale synthesis and static timing analysis in deep submicron design technologies.
Experience with design flows utilizing Unix, Linux and Verilog / System Verilog
Good knowledge and experience of working with Cadence and/or Mentor Syn/DFT tools
Excellent knowledge of working with IPs integration and related views (.Lib, ATPGLib, CTL, UPF, etc…)
Expertise in scripting skills in Perl, TCL/TK, and C shell.
Capable of assisting in determining methods and procedures to use on new projects and new design.
Candidate must possess passion and commitment for completing projects on time.