Senior VLSI Designer

Bachelor’s degree in Electrical Engineering or Computer Engineering from a leading university.
Min 4 years’ experience as VLSI front-end engineer.
Experience with Verilog and System Verilog design coding. (VHDL design is a plus)
Experience with block level verification and full chip verification. (SV verification is a plus)
Experience in gate level debug
Experience with legacy code understanding, debugging and problems solving attitude
Familiar with unix/linux and scripting languages (perl / TCL/ csh)