לוח משרות

Senior Verification Engineer

מס' המשרה: 8219
מיקום המשרה: כל הארץ
 Design, review and deploy UVM based verification environments in block level, cluster and full chip levels
דרישות:
  • 3+ years of experience in chip verification
  • In-depth Knowledge in VLSI verification flow, languages & concepts
  • A deep understanding and proven experience in advanced dynamic verification processes
  • Experience in verification environments using SystemVerilog UVM
תפריט