B.Sc. in Electrical Engineering (from known university).
Minimum 4 years of experience in SoC Verification.
Knowledge and experience in System Verilog or ‘e’ (Specman) languages.
Vast knowledge of verification flow (block level & full chip verification).
לוח משרות
Senior Verification Engineer
מס' המשרה: 5945
מיקום המשרה: השרון
This position includes hands on SOC verification tests development for full chip, cluster and block levels.
Planning and implementation of verification environments using automated tools - mainly System Verilog.
Planning and implementation of verification environments using automated tools - mainly System Verilog.
דרישות:
