In this visible role, you will be responsible to take part in the SoC VLSI design cycle from early definition through back-end implementation stage
Core Responsibilities
Your responsibilities in this role are likely to include:
Micro-architecture definitions at the unit level
RTL coding, block level simulations and synthesis
Work closely with verification team on block/top level to ensure timely delivery of quality designs
The ideal candidate will have
At least 3 years of hands on experience in VLSI Design
Must have strong Verilog / System Verliog skills
(Familiar with the various backend tools (synthesis and STA
(Familiar with advanced design practices (Clock/Voltage domain crossing, DFT and Low Power Design
Education
BS/MS in EE/CE from lead universities
